The current practice for defining poly (polysilicon) gate electrodes involves the patterning of the gate through photolithography followed by an anisotropic poly etch which stops on the gate oxide, i.e. the gate oxide acts as an etch stop. However, it has become increasingly difficult to end-point the poly etch on the gate oxide without trenching into the underlying silicon substrate as the gate oxide gets increasingly thinner. Poly edge gate oxide integrity (GOI) may become a problem if micro-trenching occurs at the poly edge.
U.S. Pat. No. 5,915,181 to Tseng describes a method of fabricating a deep submicron MOSFET (metal oxide semiconductor field effect transistor) device having a local threshold voltage adjust region in a semiconductor substrate that is self-aligned to an overlying inverse polysilicon gate structure.
U.S. Pat. No. 5,489,543 to Hong describes a method of fabricating a MOS device having a localized anti-punchthrough region that is adjacent to, but does not contact, source/drain regions. A channel ion implantation (I/I) to form the anti-punchthrough region and an inverse polysilicon gate is formed.
U.S. Pat. No. 5,786,255 to Yeh et al. describes a method of forming MOS components in that after an inverse gate and doped source/drain regions are formed, a polysilicon layer is deposited and planarized by chemical-mechanical polishing (CMP). The resulting unremoved CMP'ed poly layer acts as source/drain terminals.
U.S. Pat. No. 5,858,848 to Gardner et al. describes a method for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of an inverse gate conductor and a sacrificial dielectric sidewall.
U.S. Pat. No. 5,915,183 to Gambino et al. describes a process for forming raised source/drain junctions using chemical mechanical polishing (CMP) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by salicide gate conductors and raised shallow isolation trench regions (STI).